This invention relates to semiconductor devices and methods in manufacture and more particularly to semiconductor devices having a gate length of approximately one micron or less.
Semiconductor devices are widely used throughout the electronics industry, and the applications of semiconductor devices has dramatically increased in other areas such as games, automotive applications, industrial controls, consumer products, etc. A major reason for this increased use of semiconductor devices can be attributed to the dramatic reduction in production costs achieved by the electronics industry. For example, in the computer industry where there has been a demand for more and more storage capacity in computer memory, low cost, high density memories have been produced. In the past ten years, semiconductor memories have been developed where the number of bits of storage per semiconductor chip has been increased from 16 to 64 K. The cost per bit has been reduced by a factor of approximately 200. By increasing the density of semiconductor elements on a single chip, the manufacturing costs can be dramatically decreased. The production cost of a semiconductor memory lies particularly in the bonding, packaging, testing, and handling operations, rather than in the cost of the silicon chip which contains the actual circuitry. Therefore, any circuit which can be contained within a given chip size, for example, 300,000 square mils, will cost about the same as any other. By forming large numbers of memory cells in a single chip, the cost per bit be greatly reduced.
Since a tremendous cost reduction can be achieved by increasing the density of semiconductor device formed on a single chip, the electronic industry has focused a great deal of effort toward the design and manufacture of integrated circuits, characterized by extremely complex circuitry. Such circuits are commonly referred to as Very Large Scale Integration (VLSI) circuits. This effort of the electronics industry has resulted in the increase of dynamic random access memory storage capacity from 4 K bits per chip to 64 K bits per chip with the 64 K bit chip about the same size as the 4 K bit per chip.
The conventional approach to increasing density upon a semiconductor chip is to reduce the size of the individual semiconductor device and place more of these devices upon a single chip. Commensurate with a scaling of horizontal dimensions, the vertical thickness of the gate insulation layer, source and drain are scaled down, while substrate doping is increased. However, as device dimensions have become smaller to accommodate the higher packing density, several problems have arisen. Such problems result from the existing electrical field properties of the semiconductor devices. These include parasitic capacitances and resistances and punchthrough currents. A paper entitled "Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions" by R. H. Dennard et al., IEEE Journal of Solid State Circuits, Vol. SC-9, pp 256-268, October 1974, discusses the design, fabrication and characterization of very small MOSFET devices of one micron. Scaling relationships are presented that show how this reduction is accomplished. Techniques such as high resolution optical lithography, electron beam pattern writing and X-ray lithography are suggested in forming integrated circuit patterns. Undesirable changes in the device characteristics occur when source to drain spacing is reduced. These changes become significant when depletion regions, surrounding the source and drain, extend over the silicon substrate region under the gate and merge. This paper suggests that those short-channel effects can be avoided by scaling down the vertical dimensions of the FET such as gate insulator thickness and junction depth along with reducing the horizontal dimensions while also proportionately decreasing the applied voltages and increasing the substrate doping concentration. Specifically the doping profile of the channel region is increased to control these short-channel effects in MOSFET switching devices.
The other problem in scaling down the dimensions of the semiconductor device is parasitic current conduction. Parasitic current condition is affected by the depletion layers that surround the source and the drain region in the substrate. These depletion layers are directly affected by the voltage on the device and also by the doping of the substrate. If these depletion layers merge or overlap, then a condition called "punchthrough" can exist. Punchthrough is a phenomenon where a current between the source and the drain is present in such a manner that it is not controlled by the gate. A paper entitled, "Short Channel MOSFET's in the Punchthrough Current Mode" by John J. Barnes et al., IEEE Transactions on Electron Devices, Vol. ED-26, No. 4, April 1979, specifically addresses this punchthrough phenomenon. This paper discusses mathematical models that are used to predict punchthrough and further details the results of the experimentations that support the validity of these mathematical models. Techniques for preventing punchthrough were also discussed. These techniques include increasing the range of the doping profile, increasing the substrate concentration and/or double ion implantation in the channel. All of these techniques have certain adverse affects, for example, the increase of substrate sensitivity of threshold voltage, the increase of junction capacitance, source-and-drain line resistance, and the requirement of additional processing steps. Another paper entitled, "VLSI Limitations from Drain-Induced Barrier Lowering" by Ronald L. Troutman in IEEE Transactions on Electron Devices, Vol. ED-26, No. 4, April 1979, discusses punchthrough as an electrical limitation to scaling. This paper states that punchthrough is more likely to occur in semiconductor devices when the source or drain diffusions are deep, the substrate resistivity is high or the spacing between the source and the drain diffusions is minimal. The distance between the source and the drain diffusions is the channel length. However, as the physical channel length is reduced, the electrical length of a channel can be effectively increased by increasing the boundaries between these source and drain depletion layers which in turn can be accomplished by ion implantation in the channel or the use of low doped source and drain diffusions or recessing the channel into the substrate. Such solutions were proposed by F. Gaensslen in IBM Journal of Research and Development, Vol. 23, No. 6, pp 682-668, November 1979. Double ion implantation was also suggested as a solution to increasing a threshold voltage characteristic of a semiconductor device in a paper entitled, "Double Bond Implant Short-channel MOSFET" by Paul P. Wang, in IEEE Transactions on Electron Devices, Vol ED-24, No. 3, March 1977. The specific solution suggested was a shallow ion implant in the channel region between the source and the drain areas followed by a deeper implant which would be used to reduce the susceptibility of the device to punchthrough. This technique may be used with the disclosed invention to improve the threshold characteristics and reduce the susceptibility of the device to punchthrough. However, the double ion implant of the channel region would have to be performed prior to the formation of the gate.
Ideally the solution to both punchthrough and parasitic capacitance would be to fabricate a region of source and drain diffusion that is very shallow and also has low resistance. However, as the diffusion regions become shallow, the sheet resistance of these regions becomes increasingly large. In addition, reliable metallurgical contact to shallow source and drain regions is difficult. A solution would be to implant a shallow region of the source and drain adjacent to the gate and to use lithographically defined masking in the region near and including the gate to implant a deeper souce and drain region into regions more distant from the gate. This would result in low sheet resistance and ease of making metallurgical contact in regions distant from the gate. The limitation of lithographically defined masking patterns to accomplish this doubly-implanted shallow/deep source and drain are two fold. Firstly, the necessity to allow for alignment tolerances will place a limitation on the minimum distance which two gates can be placed, if, for example, a contact hole to the diffused region between them must be made. Secondly, the minimum depth of the shallow junction region next to the gate will be determined by the acceptable sheet resistance of this shallow region. Furthermore, the magnitude of this sheet resistance will be variable (again due to alignment tolerances), which implies that gain reduction of the device to this sheet resistance will also be variable, complicating the ability to do circuit design.
What is required is a device that would have a self-aligning structure. One possible solution, employing subtractive etching, was suggested in a paper entitled, "A Quadruply Self-Aligned MOS (QSA MOS) a Short Channel High Speed High Density MOSFET for VLSI" by Kuniichi Ohta, et al. appearing in the Technical Digest, pp. 581-584, IEDM, December 1979. The technique suggested comprises the formation of a silicon nitride mask over the gate structure, followed by undercutting of the polysilicon gate using subtractive etching beneath this nitride layer. The substrate is masked from the deep ion implant by the silicon nitride pattern. The resulting heavier concentration is therefore offset from the polysilicon edge by the undercut distance. After removing the silicon nitride mask, a second shallow implant, self-aligned to the silicon gate pattern is performed. The result is a shallow ion implantation around the gate region, and a deeper ion implantation self-aligned but offset to the gate-edge. It can be appreciated by those skilled in the art that control of the gate length requires a high degree control of the undercut etch process used to accomplish this scheme.